AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 93

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The Am79C976 controller will always read four bytes
for every host Expansion ROM read access. The inter-
face to the Expansion Bus is timed by an internal signal
called ROMCLK, which runs at one fourth of the fre-
quency of the external memory interface clock (ER-
CLK). Thus, when the clock select pins are configured
so that ERCLK runs at 90 MHz; ROMCLK runs at 22.5
MHz.
The time that the Am79C976 controller waits for data to
be valid is programmable. ROMTMG (CTRL0, bits 8-11
or BCR18, bits 15-12) defines the time from when the
Am79C976 controller drives ERA[19:0] with the Expan-
sion ROM address to when the Am79C976 controller
latches in the data on the ERD[7:0] inputs. The register
value specifies the time in number of ROMCLK cycles.
When ROMTMG is set to nine (the default value),
ERD[7:0] is sampled with the next rising edge of ROM-
CLK ten cycles after ERA[19:0] was driven with a new
address value. The clock edge that is used to sample
The host must program the Expansion ROM Base Ad-
dress register (ROMBASE) in the PCI configuration
space before the first access to the Expansion ROM.
The Am79C976 controller will not react to any access
to the Expansion ROM until both MEMEN (PCI Com-
mand register, bit 1) and ROMEN (PCI Expansion ROM
Base Address register, bit 0) are set to 1.
The amount of memory space that the Am79C976 de-
vice will claim for the Expansion ROM depends on the
contents of the Expansion ROM Configuration Register
(ROM_CFG), which should be loaded from the EE-
PROM. This register is included in the Am79C976 de-
vice so that the controller can accommodate ROMs of
different sizes without wasting memory space. The
8/01/00
ERA[19:0]
ROMCLK
ERD[7:0]
FLWE
FLOE
FLCS
P R E L I M I N A R Y
Am79C976
the data is also the clock edge that generates the next
Expansion ROM address. All four bytes of Expansion
ROM data are stored in holding registers.
Because Expansion ROM accesses take longer than
16 PCI bus clock cycles, the PCI access will be discon-
nected with no data transfer after 15 clocks. Subse-
quent accesses will be retried until all four bytes have
been read from the Expansion ROM.
The timing diagram in Figure 37 assumes the default
programming of ROMTMG (1001b = 9 CLK). After
reading the first byte, the Am79C976 controller reads in
three more bytes by incrementing the lower portion of
the ROM address. The PCI bus logic generates discon-
nect/retry cycles until all 32 bits are ready to be trans-
ferred over the PCI bus. When the host tries to perform
a burst read of the Expansion ROM, the Am79C976
controller will disconnect the access at the second data
phase.
ROM occupies a block of memory space that is some
power of two between 2K and 16M in size. If the ROM
requires 2
of the Expansion ROM Base Address Register in PCI
configuration space (ROMBASE) should appear to be
wired to 0. The contents of the Expansion ROM Config-
uration Register (ROM_CFG) determine how many bits
of the configuration space register are forced to 0.
Bits [15:1] of ROM_CFG correspond to bits [23:9] of
ROMBASE and bit 0 of ROM_CFG corresponds to bit
0 of ROMBASE. If a bit in ROM_CFG is set to 0, the
corresponding bit in ROMBASE is fixed at zero. If a bit
in ROM_CFG is set to 1, the corresponding bit in ROM-
n
bytes of address space, bits 1 through n-1
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