AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 302
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 302 of 309
- Download datasheet (3Mb)
INDEX-3
CSR112
CSR113
CSR114
CSR116
CSR117-121
CSR12
CSR122
CSR123
CSR124
CSR125
CSR13
CSR14
CSR15
CSR16-23
CSR2
CSR24
CSR25
CSR26-29
CSR3
CSR30
CSR31
CSR32-46
CSR4
CSR47
Missed Frame Count . . . . . . . . . . . . . . . .193
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . .193
Receive Collision Count . . . . . . . . . . . . .193
OnNow Power Mode Register . . . . . . . . .194
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . .195
Physical Address Register 0 . . . . . . . . . .184
Advanced Feature Control . . . . . . . . . . . .195
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . .195
Test Register 1 . . . . . . . . . . . . . . . . . . . . .195
MAC Enhanced Configuration Control . .196
Physical Address Register 1 . . . . . . . . . .185
Physical Address Register 2 . . . . . . . . . .185
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Reserved Locations . . . . . . . . . . . . . . . . .186
Initialization Block Address 1 . . . . . . . . .175
Base Address of Receive Ring Lower . . .187
Base Address of Receive Ring Upper . . .187
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . .187
Interrupt Masks and Deferral Control . . .175
Base Address of Transmit Ring Lower . .187
Base Address of Transmit Ring Upper . .187
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . .188
Test and Features Control . . . . . . . . . . . .177
Transmit Polling Interval . . . . . . . . . . . . .188
P R E L I M I N A R Y
Am79C976
CSR48
CSR49
CSR5
CSR50-57
CSR58
CSR59-75
CSR6
CSR7
CSR76
CSR77
CSR78
CSR79
CSR8
CSR80
CSR81-87
CSR88
CSR89
CSR9
CSR90-99
CTRL0
CTRL1
CTRL2
CTRL3
Cycle Frame . . . . . . . . . . . . . . . . . . . . . . . . . 24
Receive Poll Time Counter . . . . . . . . . . .188
Receive Polling Interval . . . . . . . . . . . . . 188
Extended Control and Interrupt 1 . . . . . . 179
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .189
Software Style . . . . . . . . . . . . . . . . . . . . .189
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .191
RX/TX Descriptor Table Length . . . . . . .181
Extended Control and Interrupt 2 . . . . . . 181
Receive Ring Length . . . . . . . . . . . . . . . . 191
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .191
Transmit Ring Length . . . . . . . . . . . . . . .191
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .191
Logical Address Filter 0 . . . . . . . . . . . . .184
DMA Transfer Counter and FIFO
Threshold Control . . . . . . . . . . . . . 191, 193
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .193
Chip ID Register Lower . . . . . . . . . . . . . . 193
Chip ID Register Upper . . . . . . . . . . . . . .193
Logical Address Filter 1 1 . . . . . . . . . . . . 84
Reserved . . . . . . . . . . . . . . . . . . . . . . . . .193
Control0 Register . . . . . . . . . . . . . . . . . . .139
Control1 Register . . . . . . . . . . . . . . . . . . .140
Control2 Register . . . . . . . . . . . . . . . . . . .143
Control3 Register . . . . . . . . . . . . . . . . . . .144
8/01/00
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