AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 208

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Bit
31-16
15-0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-12
208
Name
RES
IOBASEU
Name
RES
ROMTMG
zeros and read as undefined.
H_RESET, the value in this regis-
ter will be undefined. The settings
of this register will have no effect
on any Am79C976 controller
function. It is only included for
software compatibility with other
PCnet family devices.
Read/Write
BASEU
S_RESET or STOP.
zeros and read as undefined.
ue of ROMTMG is used to tune
the timing for all accesses to the
external Flash/EPROM.
ROMTMG defines the amount of
time that a valid address is driven
on the ERA[19:0] pins.
The register value specifies delay
in number of ROMCLK cycles,
where ROMCLK is an internal
clock signal that runs at one
fourth the speed of ERCLK.
Note: Programming ROMTNG
with a value of 0 is not permitted.
To ensure adequate expansion
ROM setup
should be set to 1 plus tACC /
(ROMCLK period), where tACC
is the access time of the expan-
sion ROM device (Flash or
EPROM). (The extra ROMCLK
cycle is added to account for the
ERA[19:0] output delay from
ROMCLK plus the ERD[7:0] set-
up time to ROMCLK.)
Reserved locations. Written as
Reserved
Reserved locations. Written as
Expansion ROM Timing. The val-
Description
Description
is
locations.
not
accessible.
time, ROMTMG
affected
P R E L I M I N A R Y
After
IO-
Am79C976
by
11
10
9
8
7
NOUFLO
RES
MEMCMD
EXTREQ
DWIO
This field is an alias of CTRL0,
bits 11-8.
Read/Write accessible. ROMT-
MG is set to the value of 1001b by
H_RESET and is not affected by
S_RESET or STOP. The default
value allows the use of an Expan-
sion ROM with an access time of
350 ns if ERCLK is running at 90
MHz.
Setting the NOUFLO bit guaran-
tees that the Am79C976 control-
ler will never suffer transmit
underflows, because the arbiter
that controls transfers to and from
the SSRAM guarantees a worst
case latency on transfers to and
from the MAC and Bus Transmit
FIFOs such that it will never un-
derflow if the complete packet
has
Am79C976
packet transmission begins.
Read/Write accessible. NOUFLO
is cleared to 0 after H_RESET or
S_RESET and is unaffected by
STOP.
No Underflow on Transmit. When
the NOUFLO bit is set to 1, the
Am79C976 controller will not
start transmitting the preamble
for a packet until the Transmit
Start Point (CTRL1, bits 16-17)
requirement has been met and
the complete packet has been
copied into the transmit FIFO.
When the NOUFLO bit is cleared
to 0, the Transmit Start Point is
the only restriction on when pre-
amble transmission begins for
transmit packets.
ros and read as undefined.
effect. Read as undefined.
Obsolete function. Writing has no
effect. Read as undefined.
bit indicates that the Am79C976
controller is programmed for
DWord I/O (DWIO) mode. When
Reserved location. Written as ze-
Obsolete function. Writing has no
Double Word I/O. When set, this
been
copied
controller
into
8/01/00
before
the