AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 45

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

ample, the memory system extends the data phase of
the first access by one wait state. The following three
data phases take one clock cycle each, which is deter-
mined by the timing of TRDY.
The BIU has two programmable features that can im-
prove the DMA performance with PCI bridges that do
not automatically stop burst transfers to align them with
cache line boundaries:
1. The Burst Alignment (BA) bit (CTRL0, bit 0). When
2. The Burst Limit Register (CTRL0, bits 3:0). This 4-
8/01/00
this bit is set, if a burst transfer starts in the middle
of a cache line, the transfer will stop at the first
cache line boundary.
bit register limits the maximum length of a burst
transfer. If the contents of this register are 0, the
burst length is limited by the amount of data avail-
able or by the amount of FIFO space available.
If the contents of this register are not zero, a burst
transfer will end when the transfer has crossed the
number of cache line boundaries equal to the con-
tents of this register.
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
2
P R E L I M I N A R Y
ADDR
0111
3
PAR
Am79C976
4
DATA
5
When the Am79C976 controller is a bus master, the cy-
cles it produces on the PCI bus may be terminated by
the target in one of three different ways: disconnect
with data transfer, disconnect without data transfer, and
target abort.
Figure 15 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP
is asserted on clock 4 to start the termination se-
quence. Data is still transferred during this cycle, since
both IRDY and TRDY are asserted. The Am79C976
controller terminates the current transfer with the deas-
sertion of FRAME on clock 5 and of IRDY one clock
later. It finally releases the bus on clock 7. The
Am79C976 controller will again request the bus after
two clock cycles, if it wants to transfer more data. The
starting address of the new transfer will be the address
of the next non-transferred data.
PAR
DATA
BE
6
DATA
PAR
7
DATA
PAR
8
PAR
9
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