AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 119

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

ister, which can be loaded from the serial EEPROM. It
is recommended that the shadow register be pro-
grammed to a value of 18h, which corresponds to 6 µs.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is read only.
Offset 3Fh
The PCI MAX_LAT register is an 8-bit register that spec-
ifies the maximum arbitration latency the Am79C976
controller can sustain without causing problems to the
network activity. The register value specifies the time in
units of 1/4 µs. The MAX_LAT register is an alias of the
Maximum Latency Shadow Register, which can be load-
ed from the serial EEPROM. It is recommended that the
shadow register be programmed to a value of 18h,
which corresponds to 6 µs.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is read only
Offset 44h
Bit
7-0
Offset 45h
Bit
7-0
Offset 46h
Note: All bits of this register are loaded from
EEPROM. The register is aliased to BCR36 for testing
purposes.
8/01/00
Name
CAP_ID
Name
NXT_ITM_PTR
list item as being the PCI Power
Management registers. This is a
read-only register whose value is
fixed at 1h.
points to the starting address of
the next capability. The pointer at
this offset is a null pointer, indi-
cating that this is the last capabil-
ity in the linked list of the
capabilities. This is a read-only
register whose content is fixed at
0.
This register identifies the linked
The Next Item Pointer Register
Description
Description
P R E L I M I N A R Y
Am79C976
Bit
15-11 PME_SPT
10
9
8-6
5
4
Name
D2_SPT
D1_SPT
RES
DSI
RES
cates the power states in which
the function may assert PME. A
value of 0b for any bit indicates
that the function is not capable of
asserting the PME signal while in
that power state.
asserted from D0.
asserted from D1.
asserted from D2.
asserted from D3hot.
asserted from D3cold. The value
read from bit(15) is the AND of
the value of BCR36, bit 15 and
the
VAUX_SENSE pin.
D2 Support. If this bit is a 1, this
function supports the D2 Power
Management State.
function supports the D1 Power
Management State.
read as zeros.
When this bit is 1, it indicates that
special initialization of the func-
tion is required (beyond the stan-
dard PCI configuration header)
before the generic class device
driver is able to use it.
Reserved location. Written and
read as zero.
Description
PME Support. This 5-bit field indi-
Bit(11) XXXX1b - PME can be
Bit(12) XXX1Xb - PME can be
Bit(13) XX1XXb - PME can be
Bit(14) X1XXXb - PME can be
Bit(15) 1XXXXb - PME can be
Read only.
Read only.
D1 Support. If this bit is a 1, this
Read only.
Reserved locations. Written and
Device
Read only.
current
Specific
state
Initialization.
of
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the