AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 305
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 305 of 309
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M
N
8/01/00
Look-Ahead Packet Processing
(LAPP) Concept . . . . . . . . . . . . . . . . . . . . .A-1
Loopback Operation . . . . . . . . . . . . . . . . . . .80
Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . .71
MAC Control Pause Frames . . . . . . . . . . . . .87
Magic Packet application . . . . . . . . . . . . . . . .3
Management Cycle Timing . . . . . . . . . . . . .278
Management Data Clock . . . . . . . . . . . . . . . .30
Management Data I/O . . . . . . . . . . . . . . . . . .30
Management Data Output Valid Delay
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Management Data Setup and Hold
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Master Abort . . . . . . . . . . . . . . . . . . . . . .49, 51
Master Bus Interface Unit . . . . . . . . . . . . . . .40
Master Cycle Data Parity Error Response . . 52
Master Initiated Termination . . . . . . . . . . . . .48
MAX_LAT_A
MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MDC Waveform . . . . . . . . . . . . . . . . . . . . .279
MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Media Access Control . . . . . . . . . . . . . . . . . .66
Media Access Management . . . . . . . . . . . . . .67
Media Independent Interface . . . . . . . . . .29, 81
Media Independent Interface (MII) . . . . . .1, 22
Medium Allocation . . . . . . . . . . . . . . . . . . . .67
Memory-Mapped Registers . . . . . . . . . . . . .122
MIB Offset . . . . . . . . . . . . . . . . . . . . . . . . . .122
MII Management Control Register
(Register 0) . . . . . . . . . . . . . . . . . . . . . . . . .B-1
MII Management Frames . . . . . . . . . . . . . . .82
MII Management Interface . . . . . . . . . . . . . .82
MII Management Registers . . . . . . . . . . . . .B-1
MII Network Status Interface . . . . . . . . . . . .82
MII Receive Frame Tagging . . . . . . . . . . . . .91
MII Receive Interface . . . . . . . . . . . . . . . . . .81
MII Transmit Interface . . . . . . . . . . . . . . . . .81
MIN_GNT_A
Miscellaneous Loopback Features . . . . . . . .80
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Network Interface . . . . . . . . . . . . . . . . . . . . .32
Network Port Manager . . . . . . . . . . . . . . . . .85
Non-Burst Read Transfer . . . . . . . . . . . . . . .42
Non-Burst Write Transfer . . . . . . . . . . . . . . .44
PCI Maximum Latency Alias Register . .160
PCI Minimum Grant Alias Register . . . .160
P R E L I M I N A R Y
Am79C976
O
P
Normal and Tri-State Outputs . . . . . . . . . . . 271
OnNow Functional Diagram . . . . . . . . . . . . 100
OnNow Wake-Up Sequence . . . . . . . . . . . . 100
Operating Ranges . . . . . . . . . . . . . . . . . . . . 266
Operation Without MMI Management
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Other Data Registers . . . . . . . . . . . . . . . . . . 104
Outline of LAPP Flow . . . . . . . . . . . . . . . . .A-2
Output and Float Delay Timing . . . . . . . . . .269
Output Tri-state Delay Timing . . . . . . . . . . 273
Output Valid Delay Timing . . . . . . . . . . . . .273
PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
PAL function . . . . . . . . . . . . . . . . . . . . . . . . . .3
PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . .25
Parity Error Response . . . . . . . . . . . . . . .39, 51
Pattern Match RAM . . . . . . . . . . . . . . . . . . 103
Pause Count Register . . . . . . . . . . . . . . . . . .161
PCI Base-Class Register Offset 0Bh . . . . . . 114
PCI Bus Interface Pins -
3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . 267
PCI Bus Interface Pins -
5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . 267
PCI Cache Line Size Register
Offset 0Ch . . . . . . . . . . . . . . . . . . . . . . . . . .115
PCI Capabilities Pointer Register
Offset 34h . . . . . . . . . . . . . . . . . . . . . . . . . .118
PCI Capability Identifier Register
Offset 44h . . . . . . . . . . . . . . . . . . . . . . . . . .119
PCI Command Register . . . . . . . . . . . . . . . . 111
PCI Command Register Offset 04h . . . . . . 111
PCI Configuration Alias registers . . . . . . . 111
PCI Configuration Registers 106, . . . .111, 245
PCI Configuration Space Layout . . . . . . . .106
PCI Data Register Offset 4Bh . . . . . . . . . . .121
PCI Device ID Register Offset 02h . . . . . . . 111
PCI Expansion ROM Base
Address Register Offset 30h . . . . . . . . . . . .117
PCI Header Type Register Offset 0Eh . . . . 115
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . 24
PCI Interrupt Line Register
Offset 3Ch . . . . . . . . . . . . . . . . . . . . . . . . . .118
PCI Interrupt Pin Register
Offset 3Dh . . . . . . . . . . . . . . . . . . . . . . . . . .118
Physical Address Register . . . . . . . . . . . . 160
INDEX-6
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