AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 59

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Note that the Am79C976 controller will always perform
a DWord transfer as long as it owns the buffer space,
even when there are less than four bytes to write. For
example, if there is only one byte left for the current re-
ceive frame, the Am79C976 controller will write a full
DWord, containing the last byte of the receive frame in
the least significant byte position (BSWP is cleared to
0, CSR3, bit 2). The content of the other three bytes is
undefined. The message byte count in the receive
descriptor always reflects the exact length of the re-
ceived frame.
In the normal DMA mode (when the Burst Alignment bit
= 0 and the Burst Limit register contents = 0) the
Am79C976 controller will continue transferring FIFO
data until the transmit FIFO is filled to its high threshold
(for read transfers) or the receive FIFO is emptied to its
low threshold (for write transfers), or until the
Am79C976 controller is preempted and the PCI La-
tency Timer is expired. The host should use the values
in the PCI MIN_GNT and MAX_LAT registers to deter-
mine the value for the PCI Latency Timer.
In the burst alignment mode (when the Burst Alignment
bit = 1) if a burst transfer starts in the middle of a cache
8/01/00
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
0111
ADD
3
DATA
PAR
4
0000
DATA
PAR
5
DATA
1110
PAR
P R E L I M I N A R Y
6
PAR
7
Am79C976
line, the transfer will stop at the first cache line
boundary.
If the contents of the Burst Limit register are not zero, a
burst transfer will end when the transfer has crossed
the number of cache line boundaries equal to the con-
tents of this register.
The exact number of total transfer cycles in the bus
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C976 controller’s bus request, and the
speed of bus operation. The TRDY response time of
the memory device will also affect the number of trans-
fers, since the speed of the accesses will affect the
state of the FIFO. The general rule is that the longer the
Bus Grant latency, the slower the bus transfer opera-
tions; the slower the clock speed, the higher the trans-
mit watermark; or the lower the receive watermark, the
longer the total burst length will be.
When a FIFO DMA burst operation is preempted, the
Am79C976 controller will not relinquish bus ownership
until the PCI Latency Timer expires.
Descriptor Management Unit
The Descriptor Management Unit (DMU) implements
the automatic initialization procedure and manages the
descriptors and buffers.
The Am79C976 controller is initialized by a combina-
tion of EEPROM register writes, direct register writes
from the PCI bus and, for compatibility with older PCnet
family products, DMA reads from an initialization block
in memory. The registers that must be programmed de-
pend on the features that are required in a particular
application. See USER ACCESSIBLE REGISTERS on
page 111 for more details.
The format of the legacy initialization block depends on
the programming of the SWSTYLE register, as de-
scribed in the Initialization Block section.
The initialization block is read when the INIT bit in
CSR0 is set. The INIT bit should be set before or con-
current with the STRT bit to ensure correct operation.
Once the initialization block has been completely read
in and internal registers have been updated, IDON will
be set in CSR0, generating an interrupt (if IENA is set).
The Am79C976 controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most signifi-
cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for Am79C976 op-
eration, together with the base addresses and length
information of the transmit and receive descriptor rings.
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