AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 25

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

By default INTA is an open-drain output. For applica-
tions that need an active-high edge-sensitive interrupt
signal, the INTA pin can be configured for this mode by
setting INTLEVEL (CMD3, bit 13 or BCR2, bit 7) to 1.
IRDY
Initiator Ready
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the Am79C976 controller is a bus master, it as-
serts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. During all read data
phases, the device asserts IRDY to indicate that it is
ready to accept the data.
When the Am79C976 controller is the target of a trans-
action, it checks IRDY during all write data phases to
determine if valid data is present on AD[31:0]. During
all read data phases, the device checks IRDY to deter-
mine if the initiator is ready to accept the data.
PAR
Parity
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C976 controller is a bus master, it gen-
erates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C976 controller operates in slave mode, it checks
parity during every address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.
PERR
Parity Error
During any slave write transaction and any master read
transaction, the Am79C976 controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C976 controller monitors PERR to see if the
target reports a data parity error.
REQ
Bus Request
The Am79C976 controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the Am79C976 controller does not request
the bus.
8/01/00
Input/Output
Input/Output
Input/Output
Input/Output
P R E L I M I N A R Y
Am79C976
RST
Reset
When RST is asserted LOW and the PG pin is HIGH,
then the Am79C976 controller performs an internal
s y s t e m
(HARDWARE_RESET, see section on RESET). Imme-
diately after the initial power up, RST must be held low
for 26µs. At any other time RST must be held low for a
minimum of 30 clock periods to guarantee that the de-
vice is properly reset. While in the H_RESET state, the
Am79C976 controller will disable or deassert all out-
puts. RST may be asynchronous to clock when as-
serted or deasserted.
Asserting RST disables all of the PCI pins except the
PME pin.
SERR
System Error
During any slave transaction, the Am79C976 controller
asserts SERR when it detects an address parity error,
and reporting of the error is enabled by setting PER-
REN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.
By default SERR is an open-drain output. For compo-
nent test, it can be programmed to be an active-high
totem-pole output.
STOP
Stop
In slave mode, the Am79C976 controller drives the
STOP signal to inform the bus master to stop the cur-
rent transaction. In bus master mode, the Am79C976
controller checks STOP to determine if the target wants
to disconnect the current transaction.
TRDY
Target Ready
TRDY indicates the ability of the target of the transac-
tion to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simul-
taneously. A data phase is completed on any clock
when both IRDY and TRDY are asserted.
When the Am79C976 controller is a bus master, it
checks TRDY during all read data phases to determine
if valid data is present on AD[31:0]. During all write data
phases, the device checks TRDY to determine if the
target is ready to accept the data.
When the Am79C976 controller is the target of a trans-
action, it asserts TRDY during all read data phases to
indicate that valid data is present on AD[31:0]. During
all write data phases, the device asserts TRDY to indi-
cate that it is ready to accept the data.
r e s e t
o f
t h e
t y p e
Input/Output
Input/Output
H _ R E S E T
Output
Input
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