AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 62

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the Am79C976 controller or the host. The OWN bit
within the descriptor status information, either TMD or
RMD, is used for this purpose.
Setting the OWN to 1 signifies that the Am79C976 con-
troller currently has ownership of this ring descriptor
and its associated buffer. Only the owner is permitted
to relinquish ownership or to write to any field in the de-
scriptor entry. A device that is not the current owner of
a descriptor entry cannot assume ownership or change
any field in the entry. A device may, however, read from
a descriptor that it does not currently own. Software
should always read descriptor entries in sequential or-
der. When software finds that the current descriptor is
62
RLE
TLE
IADR[31:16]
CSR2
Initialization
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RES
RES
PADR[31:16]
PADR[47:32]
LADRF[15:0]
RDRA[15:0]
PADR[15:0]
TDRA[15:0]
Block
MOD
RDRA[23:16]
TDRA[23:16]
IADR[15:0]
CSR1
P R E L I M I N A R Y
Buffers
Buffers
Xmt
Rcv
Am79C976
1st
desc.
RMDO
1st
desc.
TMD0
owned by the Am79C976 controller, then the software
must not read ahead to the next descriptor. The soft-
ware should wait at a descriptor it does not own until
the Am79C976 controller sets OWN to 0 to release
ownership to the software. (When LAPPEN (CSR3, bit
5) is set to 1, this rule is modified. See the LAPPEN de-
scription.
At initialization, the base address of the receive de-
scriptor ring is written to CSR24 (lower 16 bits) and
CSR25 (upper 16 bits), and the base address of the
transmit descriptor ring is written to CSR30 and
CSR31.
Figure 28 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is cleared to 0.
Buffer
Buffer
Data
Data
1
RMD1 RMD2 RMD3
1
TMD1 TMD2
N
Rcv Descriptor
M
Xmt Descriptor
Ring
Buffer
Buffer
N
Data
Data
Ring
2
2
M
TMD3
N
M
2nd
desc.
2nd
desc.
RMD0
N
TMD0
M
•
Buffer
Buffer
Data
Data
•
•
M
N
•
•
•
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