AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 48

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

RTABORT (PCI Status register, bit 12) will be set to
indicate that the Am79C976 controller has received a
target abort. In addition, SINT (CSR5, bit 11) will be set
to 1. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to 1. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
There are three scenarios besides normal completion
of a transaction where the Am79C976 controller will
terminate the cycles it produces on the PCI bus.
When the Am79C976 controller performs multiple non-
burst transactions, it keeps REQ asserted until the as-
sertion of FRAME for the last transaction. When GNT
is removed, the Am79C976 controller will finish the cur-
rent transaction and then release the bus. If it is not the
last transaction, REQ will remain asserted to regain
bus ownership as soon as possible. See Figure 1818.
48
DEVSEL
FRAME
STOP
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
P R E L I M I N A R Y
2
Am79C976
ADDR
0111
3
PAR
When the Am79C976 controller operates in burst
mode, it only performs a single transaction per bus
mastership period, where transaction is defined as one
address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
transaction. The Am79C976 controller will ignore the
deassertion of GNT and continue with data transfers,
as long as the PCI Latency Timer is not expired. When
the Latency Timer is 0 and GNT is deasserted, the
Am79C976 controller will finish the current data phase,
deassert FRAME, finish the last data phase, and re-
lease the bus. It will immediately assert REQ to regain
bus ownership as soon as possible.
When the preemption occurs after the counter has
counted down to 0, the Am79C976 controller will finish
the current data phase, deassert FRAME, finish the
last data phase, and release the bus. Note that it is im-
portant for the host to program the PCI Latency Timer
according to the bus bandwidth requirement of the
Am79C976 controller. The host can determine this bus
bandwidth requirement by reading the PCI MAX_LAT
and MIN_GNT registers.
4
DATA
0000
5
PAR
6
7
22929B19
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