AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 68

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The MAC engine implements the optional receive two
part deferral algorithm, with an InterFrameSpacing-
Par t1 (IFS1) time of 60 bit times and an Inter-
FrameSpacingPart 2 time of 36 bit times.
The Am79C976 controller will perform the two-part de-
ferral algorithm as specified in Clause 4.2.8 of IEEE Std
802.3 (Process Deference). The Inter Packet Gap
(IPG) timer will start timing the 96-bit InterFrameSpac-
ing after the receive carrier is deasserted.
During the first part deferral (InterFrameSpacingPart1 -
IFS1), the Am79C976 controller will defer any pending
transmit frame and respond to the receive message. If
carrier sense or collision is detected during the first part
of the gap, the IPG counter will be cleared to 0 contin-
uously until carrier sense and collision are both deas-
serted, at which point the IPG counter will resume the
96-bit time count once again. Once the IPG counter
reaches the IFS1 count (60-bit times), the Am79C976
controller will not defer to a receive frame if a transmit
frame is pending. Instead, when the IPG count reaches
96-bit times, the transmitter will start transmitting,
which will cause a collision. The Am79C976 controller
will complete the preamble (64-bit) and jam (32-bit) se-
quence before ceasing transmission and invoking the
random backoff algorithm.
The Am79C976 controller allows the user to program
both the IPG and the first part deferral (InterFrame-
SpacingPart1 - IFS1) through CSR125. The user can
change the IPG value from its default of 96-bit times to
compensate for delays through the external PHY de-
vice. Changing IFS1 will alter the period for which the
Am79C976 MAC engine will defer to incoming receive
frames.
CAUTION: Care must be exercised when altering
these parameters. Undesirable network activity
could result!
This transmit two-part deferral algorithm is imple-
mented as an option which can be disabled using the
DXMT2PD bit in CSR3. When DXMT2PD is set to 1,
the IFS1 register is ignored, and the value 0 is used for
the Inter FrameSpacingPart1 parameter. However, the
IPG value is still valid.
When the Am79C976 device operates in full-duplex
mode, the IPG timer starts counting when TX_EN is
de-asserted. CRS is ignored in full-duplex mode.
During the time period immediately after a transmission
has been completed, an external transceiver operating
in the 10 Mb/s half-duplex mode should generate an
SQE Test signal on the COL pin within 0.6 µs to 1.6 µSs
after the transmission ceases. Therefore, when the
68
the timer shall not be reset to ensure fair access to
the medium. An initial period shorter than 2/3 of the
interval is permissible including 0.
P R E L I M I N A R Y
Am79C976
Am79C976 controller is operating in half-duplex mode,
the IPG counter ignores the COL signal during the first
40-bit times of the inter-packet gap. This 40-bit times is
the time period in which the SQE Test message is ex-
pected.
The SQE Test was originally designed to check the in-
tegrity of the Collision Detection mechanism indepen-
dently of the Transmit and Receive capabilities of the
Physical Layer. However, MII-based PHY devices de-
tect collisions by sensing receptions that occur during
transmissions, a process that does not require a sepa-
rate level-sensing collision detection mechanism. Colli-
sion detection is therefore dependent on the health of
the receive channel. Since the Link Monitor function
checks the health of the receive channel, the SQE test
is not very useful for MII-based devices. Therefore, the
Am79C976 device does not report or count SQE Test
failures.
Collision detection is performed and reported to the
MAC engine via the COL input pin. Since the COL sig-
nal is not required to be synchronized with TX_CLK,
the COL signal must be asserted for at least three
TX_CLK cycles in order to be detected reliably.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC engine will abort the trans-
mission and append the jam sequence immediately.
The jam sequence is a 32-bit all zeros pattern.
The MAC engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to nor-
mal collisions (those within the slot time). Detection of
collision will cause the transmission to be rescheduled
to a time determined by the random backoff algorithm.
If a single retry was required, the XmtOneCollision
counter will be incremented. If more than one retry was
required, the XmtMultipleCollision counter will be incre-
mented. If all 16 attempts experienced collisions, the
XmtExcessiveCollision counter will be incremented.
After an excessive collision error, if REX_RTRY
(CMD3, bit 18) is cleared to 0, the transmit message
will be flushed from the FIFO. If the REX_RTRY bit is
set to 1, the transmitter will not flush the transmit mes-
sage from the FIFO. Instead, it will clear the back-off
logic and will restart the transmission process, treating
the data in the FIFO as a new frame.
If retries have been disabled by setting the DRTY bit in
CSR15, the MAC engine will abandon transmission of
the frame on detection of the first collision. In this case,
XmtExcessiveCollision counter will be incremented,
and the transmit message will be flushed from the
FIFO.
8/01/00