AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 51

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

During every data phase of a DMA read operation,
when the target indicates that the data is valid by as-
serting TRDY, the Am79C976 controller samples the
AD[31:0], C/BE[3:0] and the PAR lines for a data parity
error. When it detects a data parity error, the controller
sets PERR (PCI Status register, bit 15) to 1. When re-
porting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, the Am79C976
controller also drives the PERR signal low and sets
DATAPERR (PCI Status register, bit 8) to 1. The asser-
tion of PERR follows the corrupted data/byte enables
by two clock cycles and PAR by one clock cycle.
8/01/00
DEVSEL
FRAME
TRDY
C/BE
IRDY
GNT
CLK
PAR
REQ
AD
1
DEVSEL is sampled
2
ADDR
0111
P R E L I M I N A R Y
3
PAR
Am79C976
4
5
Figure 21 shows a transaction that has a parity error in
the data phase. The Am79C976 controller asserts
PERR on clock 8, two clock cycles after data is valid.
The data on clock 5 is not checked for parity, since on
a read access PAR is only required to be valid one
clock after the target has asser ted TRDY. The
Am79C976 controller then drives PERR high for one
clock cycle, since PERR is a sustained tri-state signal.
During every data phase of a DMA write operation, the
Am79C976 controller checks the PERR input to see if
the target reports a parity error. When it sees the PERR
input asserted, the controller sets PERR (PCI Status
register, bit 15) to 1. When PERREN (PCI Command
register, bit 6) is set to 1, the Am79C976 controller also
sets DATAPERR (PCI Status register, bit 8) to 1.
DATA
0000
6
PAR
7
8
9
22929B22
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