PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 84

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PSD4235G2V-10U

Manufacturer Part Number
PSD4235G2V-10U
Description
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
PSD4256G6V
Figure 39. Input to Output Disable / Enable
Table 61. CPLD Combinatorial Timing
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. CLKIN (PD1) t
84/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Symbol
Symbol
t
ARPW
t
f
t
t
t
t
t
ARP
ARD
MAX
t
t
ARD
t
t
MIN
CO
PD
ER
t
t
CH
EA
CL
H
S
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
CPLD Input to CPLD Output
Enable
CPLD Input to CPLD Output
Disable
CPLD Register Clear or
Preset Delay
CPLD Register Clear or
Preset Pulse Width
CPLD Array Delay
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
CLCL
ENABLE/DISABLE
Parameter
Parameter
= t
CH
INPUT TO
OUTPUT
INPUT
+ t
CNT
CL
.
1
)
Any Macrocell
1/(t
Conditions
Clock Input
Clock Input
Clock Input
1/(t
1/(t
Conditions
t
S
Macrocell
CH
+t
CH
S
Any
+t
+t
CO
+t
CO
CL
–10)
CL
)
)
tER
Min
18
11
11
22
Min
0
28
-10
-10
tEA
Max
22.7
29.4
45.0
Max
26
23
38
43
43
38
23
AI02863
Aloc
Aloc
+ 4
+ 4
PT
+ 4
+ 4
PT
Turbo
Turbo
+ 20
+ 20
+ 20
+ 20
+ 20
+ 20
Off
Off
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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