PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 19

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Data In
Control
Data Out
Direction
Drive Select
Input Macrocell
Enable Out
Output
Macrocells A
Output
Macrocells B
Mask
Macrocells A
Mask
Macrocells B
Flash Memory
Protection 1
Flash Memory
Protection 2
Flash Boot
Protection
JTAG Enable
PMMR0
PMMR2
Page
VM
Memory_ID0
Memory_ID1
Register Name
Port
0C
0A
00
04
06
08
20
22
A
Port
0B
0D
01
05
07
09
21
23
B
Port
1C
10
14
16
C
Port
1A
11
15
17
19
D
Port
30
32
34
36
38
E
Port
4C
40
42
44
46
F
Port
41
43
45
47
49
G
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Other
C0
C1
C2
C7
B0
B4
E0
E2
F0
F1
(1)
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address
Out
Stores data for output to Port pins, MCU I/O
output mode
Configures Port pin as input or output
Configures Port pins as either CMOS or
Open Drain
Reads Input Macrocells
Reads the status of the output enable to the I/
O Port driver
READ – reads output of Macrocells A
WRITE – loads Macrocell Flip-flops
READ – reads output of Macrocells B
WRITE – loads Macrocell Flip-flops
Blocks writing to the Output Macrocells A
Blocks writing to the Output Macrocells B
Read only – Primary Flash Sector Protection
Read only – Primary Flash Sector Protection
Read only – PSD Security and Secondary
Flash memory Sector Protection
Enables JTAG Port
Power Management Register 0
Power Management Register 2
Page Register
Places PSD memory areas in Program and/
or Data space on an individual basis.
Read only – SRAM and Primary memory size
Read only – Secondary memory type and
size
Description
PSD4256G6V
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