PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 61

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 40. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
Table 41. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MCU I/O
PLD I/O
Data Port (Port F, G)
Address Out
(Port E, F, G)
Address In
(Port A, B, C, D, F)
Peripheral I/O
(Port F)
JTAG ISP
MCU RESET Mode
80C51XA
All Other
MCUs with Multiplexed Bus
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
term (.oe) from the CPLD AND Array.
Mode
3
MCU
Declare pins only
Declare pins and
Logic equations
Selected for MCU
with non-multiplexed
bus
Declare pins only
Declare pins or Logic
equation for Input
Macrocells
Logic equations
(PSEL0 and PSEL1)
Declare pins only
Specific pin logic
level
Defined in PSDsoft
(PE3-PE0)
Address
Port E
N/A
a3-a0
(1)
(PE7-PE4)
0 (Note
N/A
N/A
1
N/A
N/A
N/A
N/A
Address
Address
Port E
a7-a4
a7-a4
Register
Control
Setting
4
)
(PF3-PF0)
Address
Port F
a3-a0
N/A
1 = output,
0 = input
(Note
(Note
N/A
1 (Note
N/A
N/A
N/A
N/A
Direction
Register
Setting
2
2
)
)
2
)
(PF7-PF4)
Address
Address
Port F
a7-a4
a7-a4
N/A
N/A
N/A
N/A
N/A
PIO bit = 1
N/A
N/A
VM Register
Setting
(a3-a0 for 8-
(PG3-PG0)
bit MCU)
Address
Address
a11-a8
a11-a8
Port G
PSD4256G6V
N/A
N/A
N/A
N/A
N/A
N/A
JTAG_Enable
N/A
JTAG Enable
(a7-a4 for 8-
(PG7-PG4)
bit MCU)
Address
a15-a12
Address
a15-a12
Port G
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