PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 40

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4256G6V
DECODE PLD (DPLD)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
Figure 13. DPLD Logic Array
Note: 1. The address inputs are A19-A4 when in 80C51XA mode
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
I /O PORTS (PORT A,B,C,F)
MCELLA.FB [7:0] (FEEDBACKS)
MCELLB.FB [7:0] (FEEDBACKS)
PGR0 -PGR7
A [ 15:0 ]
PD [ 3:0 ] (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
CNTRL [ 2:0 ]
( READ/WRITE CONTROL SIGNALS)
RESET
RD_BSY
8 Sector Select (FS0-FS15) signals for the
primary Flash memory (three product terms
each)
4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
2. Additional address lines can be brought in the PSD via Port A, B, C, D, or F.
*
(INPUTS)
(32)
(16)
(8)
(8)
(8)
(4)
(3)
(1)
(1)
(1)
1 internal SRAM Select (RS0) signal (three
product terms)
1 internal CSIOP Select (PSD Configuration
Register) signal
1 JTAG Select signal (enables JTAG-ISP on
Port E)
2 internal Peripheral Select signals (Peripheral
I/O mode).
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
RS0
CSIOP
PSEL0
PSEL1
JTAGSEL
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
˚
FS15
˚
˚
˚
˚
˚
SRAM SELECT
PERIPHERAL I/O
MODE SELECT
I/O DECODER
SELECT
4 SECONDARY
FLASH
MEMORY
SECTOR
SELECTS
16 PRIMARY
FLASH
MEMORY
SECTOR
SELECTS
AI04925B