PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 38

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4256G6V
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft, the logic is programmed into the
device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12, page 39 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 32.
The Turbo Bit in PSD
The PLDs in the PSD4256G6V can minimize pow-
er consumption by switching to standby when in-
puts remain unchanged for an extended time of
about 70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of
the PMMR0 register) automatically places the
PLDs into standby if no inputs are changing. Turn-
ing the Turbo mode off increases propagation de-
lays while reducing power consumption. See the
section entitled “POWER MANAGEMENT”, on
page 70, on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
38/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 32. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
MCU Address Bus
MCU Control Signals
Reset
Power-down
Port A Input
Macrocells
Port B Input
Macrocells
Port C Input
Macrocells
Port D Inputs
Port F Inputs
Page Register
Macrocell A Feedback
Macrocell B Feedback
Flash memory
Program Status Bit
Input Source
(1)
A15-A0
CNTL0-CNTL2
RST
PDN
PA7-PA0
PB7-PB0
PC7-PC0
PD3-PD0
PF7-PF0
PGR7-PGR0
MCELLA.FB7-FB0
MCELLB.FB7-FB0
Ready/Busy
Input Name
Number
Signals
16
of
3
1
1
8
8
8
4
8
8
8
8
1