PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 35

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

MEMORY SELECT SIGNALS
The Primary Flash Memory Sector Select (FS0-
FS15), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft. The following rules apply to
the equations for these signals:
1. Primary Flash memory and secondary Flash
2. Any primary Flash memory sector must not be
3. A secondary Flash memory sector must not be
4. SRAM, I/O, and Peripheral I/O spaces must not
5. A secondary Flash memory sector may overlap
6. SRAM, I/O, and Peripheral I/O spaces may
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
memory Sector Select signals must not be larg-
er than the physical sector size.
mapped in the same memory space as another
Flash memory sector.
mapped in the same memory space as another
secondary Flash memory sector.
overlap.
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 80C31 and compatible family of MCUs can be
configured to have separate address spaces for
Program memory (selected using Program Select
Enable (PSEN, CNTL2)) and Data memory (se-
lected using READ Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft to have an
initial value. It can subsequently be changed by
the MCU so that memory mapping can be
changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
to configure it for Boot-up and having the MCU
change it when desired.
Table 25, page 23 describes the VM Register.
Figure 8. Priority Level of Memory and I/O
Components
Highest Priority
Lowest Priority
Primary Flash Memory
Non-Volatile Memory
SRAM, I /O, or
Peripheral I /O
Secondary
Level 1
Level 2
Level 3
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