PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 23

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34, page 47 for the signals that are blocked on pins CNTL0-CNTL2.
Table 25. VM Register
Note: On RESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared on RESET.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Bit 7
not used
(set to 0)
Bit 7
not used
(set to 0)
Bit 7
Peripheral
mode
Bit Definitions:
APD Enable
PLD Turbo
PLD Array CLK
PLD MCells CLK
Bit Definitions:
PLD Array Addr
PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.
PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.
PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.
PLD Array ALE
PLD Array WRH
Bit 0-4 are active only when the device is configured in 8051 Mode.
Bit Definitions:
SR_code
Boot_Code
FL_Code
Boot_data
FL_data
Peripheral mode
Bit 6
not used
(set to 0)
Bit 6
PLD
Array WRH
Bit 6
not used
(set to 0)
0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
Note: In X A Mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Bit 5
not used
(set to 0)
Bit 5
PLD
MCells CLK
Bit 5
PLD
Array ALE
Bit 4
PLD
Array CLK
Bit 4
PLD Array
CNTL2
Bit 4
FL_data
PLD Array
CNTL1
Bit 3
Boot_data
Bit 3
PLD
Turbo
Bit 3
Bit 2
not used
(set to 0)
Bit 2
PLD Array
CNTL0
Bit 2
FL_code
Bit 1
APD
Enable
Bit 1
not used
(set to 0)
Bit 1
Boot_code
PSD4256G6V
not used
(set to 0)
PLD
Array Addr
SR_code
Bit 0
Bit 0
Bit 0
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