PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 66

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PSD4235G2V-10U

Manufacturer Part Number
PSD4235G2V-10U
Description
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
PSD4256G6V
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is in tri-state and the pin is in
input mode.
Ports A, B and C – Functionality and Structure
Ports A, B, and C have similar functionality and
structure, as shown in Figure 29. The ports can be
configured to perform one or more of the following
functions:
Figure 29. Port A, B, and C Structure
66/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MCU I/O Mode
MCELLA7-MCELLA0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
WR
WR
ENABLE PRODUCT TERM ( .OE )
CPLD -INPUT
DIR Register
DATA OUT
READ MUX
Register
D
D
D
B
P
Q
Q
DATA OUT
DATA IN
CPLD Output – Macrocells McellA7-McellA0
can be connected to Port A. McellB7-McellB0
can be connected to Port B. External Chip
Select (ECS7-ECS0) can be connected to Port
C or Port F.
CPLD Input – Via the Input Macrocells (IMC).
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain – pins PA7-PA0 can be configured
to Open Drain mode.
OUTPUT
MUX
ENABLE OUT
MACROCELL
INPUT
PORT Pin
AI04936B

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