PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 74

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4256G6V
RESET TIMING AND DEVICE STATUS AT RESET
Power-on RESET
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
after V
loads internal configurations, clears some of the
registers and sets the Flash memory into Operat-
ing mode. After the rising edge of Reset (RESET),
the PSD remains in the RESET Mode for an addi-
tional period, t
first memory access is allowed.
The PSD Flash memory is reset to the READ
Mode upon Power-up. Sector Select (FS0-FS15
and CSBOOT0-CSBOOT3) must all be Low,
WRITE Strobe (WR/WRL, CNTL0) High, during
Power-on RESET for maximum security of the
data contents and to remove the possibility of data
being written on the first edge of WRITE Strobe
(WR/WRL, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when
V
Warm RESET
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
Table 51. Status During Power-on RESET, Warm RESET, and Power-down Mode
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to ’0’ on Power-on RESET or Warm RESET.
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
NLNH
MCU I/O
PLD Output
Address Out
Data Port
Peripheral I/O
PMMR0 and PMMR2
Macrocells Flip-flop status
VM Register
All other registers
CC
Port Configuration
is below V
(minimum 150ns). The same t
CC
Register
is steady. During this period, the device
(1)
OPR
LKO
.
(maximum 120 ns), before the
NLNH-PO
Input mode
Valid after internal PSD
configuration bits are
loaded
Tri-stated
Tri-stated
Tri-stated
Cleared to 0
Cleared to 0 by internal
Power-On Reset
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to 0
Power-on RESET
Power-On Reset
(minimum 1ms)
OPR
period is
Unchanged
Input mode
Valid
Tri-stated
Tri-stated
Tri-stated
Depends on .re and .pr
equations
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to 0
needed before the device is operational after
Warm RESET. Figure 34, page 75 shows the tim-
ing of the Power-up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 51 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET and
Power-down mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the V
ing level. Once the PLD is active, the state of the
outputs are determined by equations specified in
PSDsoft.
RESET of Flash Memory Erase and Program
Cycles
An external Reset (RESET) also resets the inter-
nal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET)
terminates the cycle and returns the Flash memo-
ry to the READ Mode within a period of t
(minimum 25 s).
Warm Reset
Warm Reset
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Not defined
Tri-stated
Tri-stated
Unchanged
Depends on .re and .pr
equations
Unchanged
Unchanged
CC
Power-down Mode
Power-down Mode
ramps up to operat-
NLNH-A