PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 91

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Preliminary
Write, Erase and Program Timing
NOTES: 1.
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LVLX
AVLX
LXAX
AVWL
WHAX 1
WHAX 2
WHPV
WLMV
DVMV
AVPV
SLWL
DVWH
WHDX
WLWH
2.
3.
4.
5.
6.
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address
Invalid
Trailing Edge of WR to DPLD
Address Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
WR Valid to Port Output Valid Using
Micro Cell Register Preset/Clear
Data Valid to Port Output Valid
Using Micro Cell Register
Preset/Clear
Address Input Valid to Address
Output Delay
Any input used to select an internal PSD813F function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Assuming data is stable before active write signal.
Assuming write is active before data becomes valid.
Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Parameter
(5 V ± 10% Versions)
(Note 1)
(Note 1)
(Notes 1 and 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3 and 6)
(Note 3)
(Notes 3 and 4)
(Notes 3 and 5)
(Note 2)
Conditions
Min
20
15
35
15
35
6
8
5
8
0
-90
Max
30
55
55
25
Min
22
18
18
40
40
8
9
5
9
0
-12
Max
35
60
60
28
Min
28
10
20
20
45
45
10
11
5
0
-15
Max
38
65
65
30
PSD813F1-A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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