PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 77

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
*
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD813F1 can be enabled on Port C (see Table 34). All memory
(Flash and EEPROM), PLD logic, and PSD configuration bits may be programmed through
the JTAG interface. A blank part can be mounted on a printed circuit board and
programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
Table 34. JTAG Port Signals
Port Configuration
SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
PMMR0, 2
Micro Cells Flip
Flop status
VM Register*
All other registers
Port C Pin
MCU I/O
PLD Output
Address Out
Data Port
Peripheral I/O
Register
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TSTAT
TERR
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Tri-stated
Cleared to “0”
Cleared to “0” by
internal power on
reset
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
TMS
TDO
TCK
TDI
Power On Reset
Power On Reset
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Description
Unchanged
Depend on .re and
.pr equations
Initialized based on
the selection in
PSDsoft
Configuration Menu
Cleared to “0”
Warm Reset
Warm Reset
Input Mode
Tri-stated
Tri-stated
Tri-stated
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Tri-stated
Power Down Mode
Unchanged
Depend on .re and
.pr equations
Unchanged
Unchanged
PSD813F1-A
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