PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 36

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The
PSD813F1
Functional
Blocks
(cont.)
32
PSD813F1-A
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be
included in the Flash Memory, EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application
Note 57.
Figure 10 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
Figure 10. Page Register
RESET
R/W
D 0 - D7
D0
D1
D2
D3
D4
D5
D6
D7
REGISTER
PAGE
Q 0
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
FLASH
FLASH
FLASH
DPLD
CPLD
AND
PLD
INTERNAL
SELECTS
AND LOGIC
Preliminary