PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 59

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
*
NOTE: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD813F1 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD813F1 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register, or by the output enable product term. See the subsection on
the Direction Register in the “Port Registers” section. When the pin is configured as an
output, the content of the Data Out Register drives the pin. When configured as an input,
the microcontroller can read the port input through the Data In buffer. See Figure 25.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if equation are written for them in PSDabel.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro Cells, and/or as an
output from the CPLD’s Output Micro Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
Table 21. Port Operating Mode Settings
NA = Not Applicable
MCU I/O
PLD I/O
Data Port
(Port A)
Address Out
(Port A,B)
Address In
(Port A,B,C,D)
Peripheral I/O
(Port A)
JTAG ISP
(Note 2)
Mode
2. Any of these three methods will enable JTAG pins on Port C.
individual output enable product term (.oe) from the CPLD AND array.
Declare
pins only
Logic
equations
NA
Declare
pins only
Logic equation
for Input
Micro Cells
Logic equations
(PSEL0 & 1)
JTAGSEL
Defined In
PSDabel
JTAG Configuration
PSDconfiguration
Specify bus type
Defined In
NA*
NA
NA
NA
NA
Register
Control
Setting
NA
NA
NA
NA
NA
0
1
Direction
1 (Note 1)
1 = output,
0 = input
Register
Setting
(Note 1)
(Note 1)
NA
NA
NA
NA
PIO bit = 1
Register
Setting
VM
NA
NA
NA
NA
NA
NA
PSD813F1-A
Enable
JTAG_
Enable
JTAG
NA
NA
NA
NA
NA
NA
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