PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 35

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PSD813F1

Manufacturer Part Number
PSD813F1
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
Figure 8. 8031 Memory Modes – Separate Space Mode
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the Flash Memory, while the RD signal is
used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires
the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example,
to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM
register are set to “1”.
9.1.3.3 80C31 Memory Map Example
See Application Notes 57 and 64 for examples.
Figure 9. 80C31 Memory Mode – Combined Space Mode
RD
PSEN
VM REG BIT 3
VM REG BIT 4
VM REG BIT 1
VM REG BIT 2
VM REG BIT 0
DPLD
RD
RS0
EES0-3
FS0-7
PSEN
DPLD
RS0
EES0-3
FS0-7
CS
FLASH
OE
CS
FLASH
OE
CS
EEPROM
OE
RD
CS
EEPROM
OE
CS
SRAM
OE
PSD813F1-A
CS
SRAM
OE
31

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