PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 48

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The
PSD813F1
Functional
Blocks
(cont.)
44
PSD813F1-A
9.3 Microcontroller Bus Interface
The “no-glue logic” PSD813F1 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 17. The interface type is specified using
the PSDsoft Configuration.
Table 17. Microcontrollers and their Control Signals
**
**
**
9.3.1. PSD813F1 Interface to a Multiplexed 8-Bit Bus
Figure 17 shows an example of a system using a microcontroller with an 8-bit multiplexed
bus and a PSD813F1. The ADIO port on the PSD813F1 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port A or B. The PSD813F1 drives the ADIO data bus only
when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional
address inputs.
9.3.2. PSD813F1 Interface to a Non-Multiplexed 8-Bit Bus
Figure 18 shows an example of a system using a microcontroller with an 8-bit
non-multiplexed bus and a PSD813F1. The address bus is connected to the ADIO Port,
and the data bus is connected to Port A. Port A is in tri-state mode when the PSD813F1 is
not accessed by the microcontroller. Should the system address bus exceed sixteen bits,
Ports B, C, or D may be used for additional address inputs.
MCU
8031
80C51XA
80C251
80C251
80198
68HC11
68HC912
Z80
Z8
68330
M37702M2
Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be
configured for other I/O functions.
ALE/AS input is optional for microcontrollers with a non-multiplexed bus
Width
Data
Bus
8
8
8
8
8
8
8
8
8
8
8
CNTL0
R/W
R/W
R/W
R/W
R/W
WR
WR
WR
WR
WR
WR
CNTL1
PSEN
RD
RD
RD
RD
RD
DS
DS
E
E
E
PSEN
PSEN
PSEN
CNTL2
*
*
*
*
*
*
*
*
DBE
PC7
*
*
*
*
*
*
*
*
*
*
PD0** ADIO0
ALE
ALE
ALE
ALE
ALE
ALE
AS
AS
AS
AS
*
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
PA3-PA0 PA7-PA3
D3-D0
D3-D0
A3-A0
*
*
*
*
*
*
*
*
Preliminary
D7-D4
D7-D4
*
*
*
*
*
*
*
*
*