PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 56

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

52
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits
except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing
multiple functions per port. The ports are configured using PSDsoft Configuration or by the
microcontroller writing to on-chip registers in the CSIOP address space.
The topics discussed in this section are:
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 24. Individual Port architectures
are shown in Figures 26 through 29. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 24, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out and Micro Cell outputs, Direction and Control Registers,
and port pin input are all connected to the PDB.
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND array enable product term and the Direction Register. If
the enable product term of any of the array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction Register has sole control
of the buffer that drives the port pin.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
Ports A, B, and C have embedded Input Micro Cells (IMCs). The IMCs can be configured
as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by
the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from
the IMCs drive the PLD input bus and can be read by the microcontroller. Refer to the IMC
subsection of the PLD section.
•
•
•
•
•
Output data from the Data Out Register
Latched address outputs
CPLD Micro Cell output
External Chip Select from CPLD.
General Port Architecture
Port Operating Modes
Port Configuration Registers
Port Data Registers
Individual Port Functionality.
Preliminary