PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 42

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The
PSD813F1
Functional
Blocks
(cont.)
38
PSD813F1-A
The Output Micro Cell (OMC) architecture is shown in Figure 14. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDabel
program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input to
the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
9.2.2.1 Output Micro
Eight of the Output Micro Cells are connected to Ports A and B pins and are named as
McellAB0-7. The other eight Micro Cells are connected to Ports B and C pins and are
named as McellBC0-7. If an McellAB output is not assigned to a specific pin in PSDabel,
the Micro Cell Allocator will assign it to either Port A or B. The same is true for a McellBC
output on Port B or C. Table 16 shows the Micro Cells and Port assignment.
Table 16. Output Micro Cell Port and Data Bit Assignments
Micro Cell
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Output
Assignment
Port B0, C0
Port B1, C1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5, C5
Port B6, C6
Port B7, C7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Cell
Port
Product
Native
Terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
Maximum
Borrowed
Product
Terms
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
Data Bit for
Loading or
Reading
Preliminary
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7