MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 356

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Analog-to-Digital Converter (ADC)
17.7.2 ADC Clock Control Register
Data Sheet
356
Address:
The ADC clock control register (ADICLK) selects the clock frequency for
the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 17-2
should be set to between 500kHz and 2MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
For More Information On This Product,
Figure 17-4. ADC Clock Control Register (ADICLK)
ADIV2
$0058
ADIV2
X = don’t care
0
0
0
0
0
1
Go to: www.freescale.com
shows the available clock configurations. The ADC clock
= Unimplemented
ADIV1
Table 17-2. ADC Clock Divide Ratio
0
ADIV1
X
0
0
1
1
ADIV0
0
ADIV0
X
0
1
0
1
ADICLK
0
MODE1
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
R
MC68HC908AP Family — Rev. 2.5
0
ADC Clock Rate
= Reserved
MODE0
1
0
0
MOTOROLA
R
0
0