MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 207

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MC68HC908AP16CFA

Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
12.4 Timebase Register Description
MC68HC908AP Family — Rev. 2.5
MOTOROLA
Address:
The timebase has one register, the TBCR, which is used to enable the
timebase interrupts and set the rate.
TBIF — Timebase Interrupt Flag
TBR[2:0] — Timebase Rate Selection
Reset:
Read:
Write:
Table 12-1. Timebase Rate Selection for OSCCLK = 32.768 kHz
TBR2
This read-only flag bit is set when the timebase counter has rolled
over.
These read/write bits are used to select the rate of timebase interrupts
as shown in
Freescale Semiconductor, Inc.
0
0
0
0
1
1
1
1
For More Information On This Product,
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
$0051
TBIF
Bit 7
Figure 12-2. Timebase Control Register (TBCR)
0
TBR1
Go to: www.freescale.com
0
0
1
1
0
0
1
1
= Unimplemented
Table
TBR2
6
0
TBR0
12-1.
0
1
0
1
0
1
0
1
TBR1
5
0
Divider
262144
131072
65536
32768
TBR0
64
32
16
8
4
0
TACK
R
3
0
0
Timebase Interrupt Rate
0.125
1024
2048
4096
Timebase Register Description
0.25
512
0.5
Hz
1
= Reserved
TBIE
Timebase Module (TBM)
2
0
TBON
1
0
~0.24
8000
4000
2000
1000
~0.5
ms
Data Sheet
~2
~1
Bit 0
R
0
207

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