MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 262

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Infrared Serial Communications
14.6.3.2 Character Reception
14.6.3.3 Data Sampling
Data Sheet
262
RT CLOCK
RT CLOCK
SAMPLES
SCI_RxD
CLOCK
RESET
STATE
RT
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (IRSCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the IRSCDR. The SCI receiver full
bit, SCRF, in IRSCI status register 1 (IRSCS1) becomes set, indicating
that the received byte can be read. If the SCI receive interrupt enable bit,
SCRIE, in IRSCC2 is also set, the SCRF bit generates a receiver CPU
interrupt request.
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see
Freescale Semiconductor, Inc.
•
•
Figure 14-9. Receiver Data Sampling
QUALIFICATION
For More Information On This Product,
START BIT
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
Figure
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14-9):
VERIFICATION
START BIT
START BIT
SAMPLING
DATA
MC68HC908AP Family — Rev. 2.5
LSB
MOTOROLA