PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 513

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2011 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
W
Q1
=
Move Literal to W
MOVLW k
0  k  255
k  W
None
The eight-bit literal ‘k’ is loaded into W.
1
1
literal ‘k’
MOVLW
Read
0000
Q2
5Ah
1110
5Ah
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
Preliminary
PIC18F66K80 FAMILY
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
Move W to f
MOVWF
0  f  255
a  [0,1]
(W)  f
None
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f  95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
MOVWF
Read
0110
Q2
4Fh
FFh
4Fh
4Fh
REG, 0
f {,a}
111a
Process
Data
Q3
DS39977C-page 513
ffff
for details.
register ‘f’
Write
Q4
ffff