PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 289

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 20-5:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
CMPL1
R/W-0
The PWM Steering mode is available only when the CCP1CON register bits, CCP1M<3:2> = 11 and
P1M<1:0> = 00 .
CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
00 = See STR<D:A>.
01 = PA and PB are selected as the complementary output pair
10 = PA and PC are selected as the complementary output pair
11 = PA and PD are selected as the complementary output pair
Unimplemented: Read as ‘ 0 ’
STRSYNC: Steering Sync bit
1 = Output steering update occurs on the next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
CMPL0
R/W-0
PSTR1CON: PULSE STEERING CONTROL
W = Writable bit
‘1’ = Bit is set
U-0
—
STRSYNC
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
R/W-0
STRD
(1)
R/W-0
STRC
x = Bit is unknown
R/W-0
STRB
DS39977C-page 289
R/W-1
STRA
bit 0