PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 192

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
TABLE 11-7:
TABLE 11-8:
DS39977C-page 192
RD7/RX2/DT2/
P1D/PSP7
Legend:
Note 1:
PORTD
LATD
TRISD
PADCFG1
ODCON
ANCON1
Legend: Shaded cells are not used by PORTD.
Note 1:
Pin Name
Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pin assignment for 40 and 44-pin devices (PIC18F4XK80).
Unimplemented on 28-pin devices, read as ‘ 0 ’.
Unimplemented on 28/40/44-pin devices, read as ‘ 0 ’.
RDPU
TRISD7
SSPOD
LATD7
Bit 7
RD7
PORTD FUNCTIONS (CONTINUED)
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
—
RX2
DT2
PSP7
RD7
P1D
(1)
(1)
(1)
ANSEL14
CCP5OD
REPU
TRISD6
LATD6
Bit 6
RD6
Setting
TRIS
0
1
1
1
1
0
x
(1)
ANSEL13
CCP4OD
I/O
I/O
RFPU
TRISD5
O
O
O
LATD5
I
I
I
Bit 5
RD5
I/O Type
(2)
DIG
DIG
DIG
ST
ST
ST
ST
Preliminary
ANSEL12
CCP3OD
RGPU
TRISD4
LATD4
LATD<7> data output.
PORTD<7> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
ECCP1 Enhanced PWM output, Channel D. May be configured for
tri-state during Enhanced PWM.
Parallel Slave Port data.
Bit 4
RD4
(2)
ANSEL11
CCP2OD
TRISD3
LATD3
Bit 3
RD3
—
ANSEL10
CCP1OD
TRISD2
LATD2
Description
Bit 2
RD2
—
 2011 Microchip Technology Inc.
ANSEL9
TRISD1
LATD1
U2OD
Bit 1
RD1
—
CTMUDS
ANSEL8
TRISD0
LATD0
U1OD
Bit 0
RD0