PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 162

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
REGISTER 10-8:
DS39977C-page 162
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
IRXIF
IRXIF: Invalid Message Received Interrupt Flag bits
1 = An invalid message occurred on the CAN bus
0 = No invalid message occurred on the CAN bus
WAKIF: Bus Wake Up Activity Interrupt Flag bit
1 = Activity on CAN bus has occurred
0 = No activity on CAN bus
1 = An error has occurred in the CAN module (multiple sources)
0 = No CAN Module errors
TXB2IF: Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
TXB1IF: Transmit Buffer 1 Interrupt Flag bit
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
TXB0IF: Transmit Buffer 0 Interrupt Flag bit
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
RXB1IF: Receive Buffer 1 Interrupt Flag bit
Mode 0:
1 = CAN Receive Buffer 1 has received a new message
0 = CAN Receive Buffer 1 has not received a new message
Modes 1 and 2:
1 = A CAN Receive Buffer/FIFO has received a new message
0 = A CAN Receive Buffer/FIFO has not received a new message
Bit operation is dependent on selected mode:
Mode 0:
RXB0IF: Receive Buffer 0 Interrupt Flag bit
1 = CAN Receive Buffer 0 has received a new message
0 = CAN Receive Buffer 0 has not received a new message
Mode 1:
Unimplemented: Read as ‘ 0 ’
Mode 2:
FIFOFIF: FIFO Full Interrupt Flag bit
1 = FIFO has reached full status as defined by the FIFO_HF bit
0 = FIFO has not reached full status as defined by the FIFO_HF bit
ERRIF: Error Interrupt Flag bit (Multiple sources in COMSTAT register)
WAKIF
R/W-0
PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5
W = Writable bit
‘1’ = Bit is set
ERRIF
R/W-0
TXB2IF
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXB1IF
R/W-0
TXB0IF
R/W-0
 2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IF
R/W-0
RXB0IF/
FIFOFIF
R/W-0
bit 0