PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 510

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39977C-page 510
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR Literal with W
IORLW k
0  k  255
(W) .OR. k  W
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
1
1
literal ‘k’
IORLW
Read
0000
Q2
9Ah
BFh
1001
35h
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
Preliminary
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0  f  255
d  [0,1]
a  [0,1]
(W) .OR. (f)  dest
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘ 0 ’, the result is placed in W. If ‘d’ is ‘ 1 ’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f  95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
 2011 Microchip Technology Inc.
RESULT, 0, 1
f {,d {,a}}
00da
Process
Data
Q3
ffff
for details.
destination
Write to
Q4
ffff