PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 467

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 28-5:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
MCLRE
R/P-1
Implemented only on the 64-pin devices (PIC18F6XK80). Maintain as ‘ 0 ’ on 28-pin, 40-pin and 44-pin
devices.
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RE3 input pin is disabled
0 = RE3 input pin is enabled; MCLR is disabled
Unimplemented: Read as ‘ 0 ’
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
T3CKMX: Timer3 Clock Input MUX bit
1 = Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages
0 = Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages
T0CKMX: Timer0 Clock Input MUX bit
1 = Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages
0 = Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages
CANMX: ECAN MUX bit
1 = CANTX and CANRX pins are located on RB2 and RB3, respectively
0 = CANTX and CANRX pins are located on RC6 and RC7, respectively (28-pin and 40/44-pin
packages) or on RE4 and RE5, respectively (64-pin package)
U-0
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
Preliminary
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MSSPMSK
PIC18F66K80 FAMILY
R/P-1
T3CKMX
R/P-1
(1)
x = Bit is unknown
T0CKMX
R/P-1
DS39977C-page 467
(1)
CANMX
R/P-1
bit 0