PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 301

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

21.3.9
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of the Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (SOSC oscillator) or the INTOSC
source. See
Oscillator Switching”
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupt is enabled, it can wake the controller
from Sleep mode, or one of the Idle modes, when the
master completes sending data. If an exit from Sleep or
Idle mode is not desired, MSSP interrupts should be
disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
TABLE 21-2:
 2011 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISA
TRISC
SSPBUF
SSPCON1
SSPSTAT
ODCON
PMD0
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Name
and
OPERATION IN POWER-MANAGED
MODES
data
MSSP Receive Buffer/Transmit Register
Section 3.3 “Clock Sources and
GIE/GIEH PEIE/GIEL
CCP5MD
TRISC7
TRISA7
SSPOD
PSPIF
PSPIE
PSPIP
WCOL
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
SMP
to be
for additional information.
CCP5OD
CCP4MD
TRISA6
TRISC6
SSPOV
shifted into
ADIE
ADIP
Bit 6
ADIF
CKE
CCP4OD
CCP3MD
TMR0IE
TRISA5
TRISC5
SSPEN
RC1IE
RC1IP
RC1IF
Bit 5
D/A
the
SPI
Preliminary
CCP2MD
CCP3OD
TRISC4
INT0IE
TX1IF
TX1IE
TX1IP
Bit 4
CKP
—
P
PIC18F66K80 FAMILY
21.3.10
A Reset disables the MSSP module and terminates the
current transfer.
21.3.11
Table 21-1
standard SPI modes, and the states of the CKP and
CKE control bits.
TABLE 21-1:
There is also an SMP bit which controls when the data
is sampled.
Standard SPI Mode
CCP1MD
CCP2OD
TRISC3
TRISA3
SSPM3
SSPIF
SSPIE
SSPIP
Terminology
RBIE
Bit 3
S
0, 0
0, 1
1, 0
1, 1
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
shows the compatibility between the
UART2MD
TMR1GIF
TMR1GIE
TMR1GIP
CCP1OD
TMR0IF
TRISC2
TRISA2
SSPM2
SPI BUS MODES
Bit 2
R/W
CKP
UART1MD
Control Bits State
TMR2IF
TMR2IE
TMR2IP
TRISC1
TRISA1
SSPM1
0
0
1
1
INT0IF
U2OD
Bit 1
UA
DS39977C-page 301
TMR1IF
TMR1IE
TMR1IP
TRISA0
TRISC0
SSPMD
SSPM0
CKE
U1OD
RBIF
Bit 0
1
0
1
0
BF