PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 306

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
REGISTER 21-6:
REGISTER 21-7:
DS39977C-page 306
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
R/W-0
GCEN
R/W-1
MSK7
2:
If the I
writes to the SSPBUF are disabled).
This register shares the same SFR address as SSPADD and is only addressable in select MSSP
operating modes. See
MSK0 is not used as a mask bit in 7-bit addressing.
GCEN: General Call Enable bit
1 = Enables interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Stretch Enable bit
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
MSK<7:0>: Slave Address Mask Select bit
1 = Masking of corresponding bit of SSPADD enabled
0 = Masking of corresponding bit of SSPADD disabled
ACKSTAT
2
R/W-1
C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
R/W-1
MSK6
Automatically cleared by hardware.
SSPCON2: MSSP CONTROL REGISTER 2 (I
SSPMSK: I
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
R/W-1
MSK5
Section 21.4.3.4 “7-Bit Address Masking Mode”
2
C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
(1)
(1)
ACKEN
(1)
2
C™
R/W-0
R/W-1
MSK4
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
RCEN
R/W-0
R/W-1
MSK3
(1)
(1)
2
(1)
C™ SLAVE MODE)
PEN
R/W-0
R/W-1
MSK2
(1)
for more details.
 2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
RSEN
R/W-0
R/W-1
MSK1
(1)
MSK0
SEN
R/W-0
R/W-1
(1)
(2)
bit 0
(1)
bit 0