PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 440

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
DS39977C-page 440
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
In CAN Mode 1 and 2, these bits are forced to ‘ 0 ’.
bit 7
IRXIP: CAN Bus Error Message Received Interrupt Priority bi t
1 = High priority
0 = Low priority
WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
ERRIP: CAN Module Error Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1 = High priority
0 = Low priority
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘ 0 ’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1 = High priority
0 = Low priority
R/W-x
R/W-x
IRXIP
IRXIP
WAKIP
WAKIP
R/W-x
R/W-x
W = Writable bit
‘1’ = Bit is set
ERRIP
ERRIP
R/W-x
R/W-x
Preliminary
TXB2IP
TXBnIP
R/W-x
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
(1)
TXB1IP
TXB1IP
R/W-x
R/W-x
(1)
(1)
TXB0IP
TXB0IP
R/W-x
R/W-x
(1)
(1)
 2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IP
RXBnIP
R/W-x
R/W-x
FIFOWMIP
RXB0IP
R/W-x
R/W-x
bit 0