SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 37

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
10. I
SC16IS740_750_760_5
Product data sheet
2
C-bus operation
10.1 Data transfers
The two lines of the I
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see
free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit.
(see
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Figure
Fig 16. Bit transfer on the I
Fig 17. START and STOP conditions
Figure
SDA
SCL
19).
18). The clock pulse related to the acknowledge bit is generated by the
Figure
START condition
SDA
SCL
S
2
Rev. 05 — 16 November 2006
Single UART with I
C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
17). The bus is considered to be busy after the START condition and
2
C-bus
data valid
data line
stable;
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
allowed
change
of data
SC16IS740/750/760
Figure
STOP condition
16). The data on the SDA
mba607
P
© NXP B.V. 2006. All rights reserved.
mba608
SDA
SCL
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