SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 32

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
8.12 Transmission Control Register (TCR)
8.13 Trigger Level Register (TLR)
8.14 Transmitter FIFO Level register (TXLVL)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control.
settings.
Table 23.
TCR trigger levels are available from 0 to 60 characters with a granularity of four.
Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before auto RTS or software flow control is enabled to avoid spurious operation
of the device.
This 8-bit register is used to store the transmit and received FIFO trigger levels used for
interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of
4.
Table 24.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters
to 60 characters are available with a granularity of four. The TLR should be programmed
for
When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger
level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level
defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger
level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
that is, ‘00’.
This register is a read-only register, it reports the number of spaces available in the
transmit FIFO.
Table 25.
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7
6:0
Table 24
N
4
, where N is the desired trigger level.
Symbol
TCR[7:4]
TCR[3:0]
Symbol
TLR[7:4]
TLR[3:0]
Symbol
-
TXLVL[6:0]
Transmission Control Register bits description
Trigger Level Register bits description
Transmitter FIFO Level register bits description
shows trigger level register bit settings.
Rev. 05 — 16 November 2006
Single UART with I
Description
RX FIFO trigger level to resume
RX FIFO trigger level to halt transmission
Description
RX FIFO trigger levels (4 to 60), number of characters available.
TX FIFO trigger levels (4 to 60), number of spaces available.
Description
not used; set to zeros
number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)
Table 23
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
shows Transmission Control Register bit
SC16IS740/750/760
© NXP B.V. 2006. All rights reserved.
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