SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 29

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
8.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation.
Table 19.
[1]
[2]
Bit
7
6
5
4
3
2
1
0
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
Only available on the SC16IS750/SC16IS760.
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Table 19
[1]
[1]
[1]
[1]
Description
CTS interrupt enable
RTS interrupt enable
Xoff interrupt
Sleep mode
Modem Status Interrupt
Remark: See IOControl register bit 1 for the description of how to program the
pins as modem pins.
Receive Line Status interrupt
Transmit Holding Register interrupt.
Receive Holding Register interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
Rev. 05 — 16 November 2006
shows the Interrupt Enable Register bit settings.
Single UART with I
[2]
.
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
Section 7.6 “Sleep mode”
© NXP B.V. 2006. All rights reserved.
for details.
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