SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 34

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
8.19 I/O Control register (IOControl)
This register is only available on the SC16IS750 and SC16IS760.
Table 30.
Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled
by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI,
DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these
three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the
state of the DTR pin cannot be controlled by MCR[0].
As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of DTR pin can be controlled by MCR[0]. Also, if
modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will
trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not
have any effect on these three pins.
Bit
7:4
3
2
1
0
Symbol
-
SRESET
-
GPIO[7:4] or
modem pins
IOLATCH
IOControl register bits description
Rev. 05 — 16 November 2006
Single UART with I
Description
reserved for future use
software reset
reserved for future use
This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR
pins.
enable/disable inputs latching
A write to bit will reset the device. Once the device is reset this bit is
automatically set to ‘0’
0 = GPIO[7:4] behave as I/O pins
1 = GPIO[7:4] behave as RI, CD, DTR, DSR
0 = input values are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
© NXP B.V. 2006. All rights reserved.
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