SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 31

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
8.10 Enhanced Features Register (EFR)
8.11 Division registers (DLL, DLH)
This 8-bit register enables or disables the enhanced features of the UART.
the enhanced feature register bit settings.
Table 22.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced Features Register bits description
Description
CTS flow control enable
RTS flow control enable.
Special character detect
Enhanced functions enable bit
Combinations of software flow control can be selected by programming these
bits. See
Rev. 05 — 16 November 2006
Single UART with I
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO resume transmission trigger level TCR[7:4] is reached.
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to FIFO
and IIR[4] is set to a logical 1 to indicate a special character has been
detected.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
so that they can be modified.
Table 3 “Software flow control options
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
(EFR[3:0])”.
© NXP B.V. 2006. All rights reserved.
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