SC16IS740IPW PHILIPS [NXP Semiconductors], SC16IS740IPW Datasheet - Page 17

• Manufacturer Part Number: SC16IS740IPW
• Description: Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
7.6 Sleep mode
7.7 Break and time-out conditions
7.8 Programmable baud rate generator
Sleep mode is an enhanced feature of the SC16IS740/750/760 UART. It is enabled when
EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered
when:
Remark: Sleep mode will not be entered if there is data in the RX FIFO.
In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using
these clocks, the power consumption is greatly reduced. The UART will wake up when any
change is detected on the RX line, when there is any change in the state of the modem
input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLH.
When the UART receives a number of characters and these data are not enough to set off
the receive interrupt (because they do not reach the receive trigger level), the UART will
generate a time-out interrupt instead, 4 character times after the last character is
received. The time-out counter will be reset at the center of each stop bit received or each
time the receive FIFO is read.
A break condition is detected when the RX pin is pulled LOW for a duration longer than
the time it takes to send a complete character plus Start, Stop and Parity bits. A break
condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW
until LSR[6] is cleared by the software.
The SC16IS740/750/760 UART contains a programmable baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (2
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as
shown in
The formula for the divisor is:
where:
Remark: The default value of prescaler after reset is divide-by-1.
divisor
•
•
•
prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).
The serial data input line, RX, is idle (see
conditions”).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR.
=
Figure
----------------------------------------------------------------------------------------- -
XTAL1 crystal input frequency
------------------------------------------------------------------------------------ -
14. The output frequency of the baud rate generator is 16 the baud rate.
desired baud rate 16
Rev. 05 — 16 November 2006
Single UART with I
prescaler
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Section 7.7 “Break and time-out
SC16IS740/750/760
© NXP B.V. 2006. All rights reserved.
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