CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 89

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Note. For 576-bit searches, the host ASIC must supply individual 72-bit data on DQ[71:0] during cycles A and B. Also, four
individual pairs of GMR and CMPR registers may be involved in the comparison.
The logical 576-bit Search operation is shown in Figure 6-34. The entire table of 576-bit entries (eight devices) is compared to a
576-bit word K that is presented on the DQ bus in eight cycles using the GMR and local mask bits. The GMR is the 576-bit word
specified by four pairs of GMRs selected by GMR indices in each of the eight devices. The 576-bit word K (presented on the DQ
bus in all eight cycles of the command) is also stored in both even and odd comparand register pairs (selected by the comparand
register index in command cycle B) in each of the eight devices. The word K is compared with each entry in the table, starting at
location 0 (decimal). A matching entry that satisfies the Soft Priority and Mini-Key scheme will be the winning entry, and its location
address L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on
page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The global winning device will drive the bus in
a specific cycle. On a global miss cycle, the device with LRAM = 1 (binary) (default driving device for the SRAM bus) and LDEV = 1
(binary) (default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at one-eighth the rate of the frequency of CLK2X for 576-bit
searches in ×576-configured tables. The latency of the Search from command to SRAM access cycle is 5 for up to eight devices
in the table (TLSZ = “01” (binary)). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
6.5.7
The MultiSearch operates the search commands in parallel on the upper and lower half (array 0 and 1) of the device. The results
from the two parallel searches are then driven on the SRAM bus at twice that rate relative to a single-search.
Notes:
Document #: 38-02069 Rev. *F
• Cycle B:
• For x72 multi searches, two individual 72-bit search keys can be searched in array 0 and array 1 simultaneously. For x144,
x288 and x576 multi searches, both arrays will be searched with the same 144-bit, 288-bit or 576-bit search keys respectively.
Will be same in each of the eight
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with 72-bit data (which is part of the 576-bit data) to be
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data (which is part of the 576-bit data) to be compared.
Comparand Register (Odd)
Comparand Register (Even)
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. Each of the
four A-cycles provide a GMR index to mask 144 bits of the data to be compared (each A-cycle provide a pair of GMR, which
is 144 bits, for A-cycles will result in a total of 576 bits of GMR). CMD[8:6] signals must be driven with the same bits that
will be driven on SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 by this
device if it has a hit. CMD[9] is don’t care for this cycle.
compared.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the
DQ bus during cycles A and B. Each of the four B-cycles provide an index for a pair of comparand register. CMD[8:6] signals
must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag (see
page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
71
576-bit MultiSearch for One Device or Cascade up to Eight Devices
devices
Must be same in each
of the eight devices
K
K
0
Location
address
Figure 6-34. ×576 Table with Eight Devices
GMR
N
0
1
2
3
L
K
576
576
CONFIDENTIAL
PRELIMINARY
(576-bit configuration)
N = 262143 for CYNSE10512
0
131071 for CYNSE10256
65535 for CYNSE10128
0
CYNSE10512
CYNSE10256
CYNSE10128
(First matching
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