CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 45

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.9.2
The following table (Table 5-27) details the parameters expected (in DQ bus) to access the internal registers of the NSE.
Table 5-27. Internal Register Address Space Encoding
5.10
The NSE application can depth-cascade the devices to various table sizes of different widths (72-bit, 144-bit, 288-bit or 576-bit).
The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. Some operations and features
are not cascadable, which means that the operation or feature is on a device-by-device basis and the results are not propagated
to the next device. Table 5-28 lists those operations and features. The following subsections covers the interconnects when the
devices in a cascade operates in the Non-Enhanced mode or Enhanced Mode with MSE set to 0 (MultiSearch disabled). For
device interconnects when operating in Enhanced mode with MultiSearch enabled, please refer to Figure 6-14.
Table 5-28. Cascadability of Operations and Features
5.10.1
Figure 5-32 shows the interconnection of up to eight devices in a cascade to form 2M × 72, 1M × 144, 512K × 288, or 256K x
576 tables. Each NSE asserts the LHO[1] and LHO[0] signals to inform downstream devices of its result. LHI[6:0] signals for a
device are connected to LHO signals of the upstream devices. The host ASIC must program the TLSZ to 01 (binary) for each of
up to eight devices in a block. Only a single device drives the SRAM bus in any single cycle.
Note:
Document #: 38-02069 Rev. *F
13. Software solutions are possible for these cases. Please refer to specific application notes.
MultiSearch Command
Learn Command
Soft Priority
FULL
MULTI_HIT
INDIRECT
BLKNUM
REGSEL
Operations / # of Devices
CHIPID
RSEL
Field
Addressing the Internal Registers
71
Depth Cascading
Depth Cascading up to Eight Devices in One Block
63
(decimal)
Range
[17:11]
[20:19]
[25:21]
[28:26]
[71:30]
[10:0]
[18]
[29]
55
Figure 5-31. Internal Register Address Space Encoding
Register Address Selected. This field selects which internal register to address.Table 5-
3 lists the registers that are available.
Block Number. This field selects the block within the device that will participate in the
operation. It is only used when accessing block specific internal registers (BMR, BPR,
BPAR, BNFA and BPRA0-3). For other internal register accesses, this field must be set to 0.
Reserved.
Register Area Select. This field indicates in what context the access takes place. It must
be set to “11”.
Device ID. This field indicates which NSE device should respond to the READ or WRITE
operation. CHIPID value “11111” indicates a broadcast operation.
Reserved.
Indirect Addressing Enable. This bit must be cleared to 0.
Reserved.
Yes
Yes
Yes
No
No
1
Non-Enhanced
47
Yes
Yes
2-8
No
No
No
CONFIDENTIAL
PRELIMINARY
39
9-31
No
No
No
No
No
31
Yes
Yes
Yes
Yes
No
1
Enhanced Mode
with MSE = 0
Description
No
CHIPID
Yes
Yes
2-8
No
No
23
[13]
No
No
9-31
No
No
No
[13]
[13]
BLKNUM
15
Yes
Yes
Yes
Yes
Yes
1
Enhanced Mode
CYNSE10512
CYNSE10256
CYNSE10128
with MSE = 1
REGSEL
7
No
No
Yes
2-8
No
No
Page 45 of 153
[13]
[13]
0
No
No
9-31
No
No
No
[13]
[13]
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