CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 125

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.7.3
The following explains the SRAM Read operation accomplished through a table of up to 31 devices, using the following parameter:
TLSZ = 10 (binary). The hardware diagram is shown in Figure 6-67. The following assumes that SRAM access is being accom-
plished through Ayama 10000 device number 0, and that device number 0 is the selected device. Figure 6-68 and Figure 6-69
show the timing diagrams for device number 0 and device number 30, respectively.
At the end of cycle 10, the selected device floats ACK to High-Z and a new command can begin.
Document #: 38-02069 Rev. *F
• Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0], using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0].
• Cycles 5 to 6: The selected device continues to drive DQ[71:0].
• Cycle 7: The selected device continues to drive DQ[71:0], and drives an SRAM Read cycle.
• Cycle 8: The selected device drives ACK from Z to LOW.
• Cycle 9: The selected device drives ACK to HIGH.
• Cycle 10: The selected device drives ACK from HIGH to LOW.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256,
SADR[23:21] for CYNSE10128 on CMD[8:6].
address, with DQ[20:19] set to 10, to select the SRAM address.
TLSZ = 01
SRAM Read with a Table of up to 31 Devices
(binary)
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
SADR
, HLAT = 000
WE_L
OE_L
CE_L
ACK
SSV
SSF
Figure 6-66. SRAM Read Timing of Device #7 in a Block of Eight Devices
DQ
(binary)
0
1
1
1
z
z
z
z
, LRAM = 1
cycle
1
Address
A
Read
CONFIDENTIAL
PRELIMINARY
B
(binary)
cycle
2
z
, LDEV = 1
cycle
3
(binary)
cycle
4
cycle
5
cycle
6
z
z
z
z
1
1
1
CYNSE10512
CYNSE10256
CYNSE10128
Page 125 of 153
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